This invention relates to a fabrication process for forming conductive lines for semiconductor devices and particularly to a process to form metal lines for semiconductor memory devices.
In semiconductor devices, conductive lines are used to interconnect between various devices, between circuitry, or between both. For example, power buses are typically made of a metal that is capable of carrying the required current necessary to operate the device.
In a semiconductor memory device, besides metal power buses, the memory array is interconnected by a grid of column (digit or bit) and row (word) lines. The word lines are typically made of polycrystalline silicon (also know as polysilicon or poly), and topped with a metal silicide, while the bit lines comprise some form of metal.
The bit lines, in a memory array, run basically perpendicular to the word lines and in a parallel fashion to one another. A common characteristic between neighboring bit lines is the capacitive coupling that exists. Digit lines need to be at a specific precharge voltage in order to be read correctly during memory cell sensing. There is a capacitive coupling component between neighboring conductors in many conventional memory array devices, with the result that when a neighboring digit line is pulled high or low, it can couple a digit line above or below the precharge voltage, thus affecting the device""s ability to sense data correctly. As memory arrays become denser, the bit lines are crowded even closer together, which in turn will tend to increase the capacitive coupling.
It is desirable to reduce the capacitive coupling between conductive lines and in particular between neighboring bit lines of a memory array in order to provide a more efficient array. The present invention discloses a method to form a conductive line configuration that may be used in any semiconductor device which uses substantially parallel conductors, such as in the memory array of a memory device, or the like, that indeed reduces capacitive coupling between neighboring conductive lines (i.e., neighboring bit lines in a memory array).
The present invention includes a method for forming conductive lines fabricated in a semiconductor device. In a preferred implementation, the method includes the steps of forming a first layer of patterned conductive lines, which have substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines are formed by a double metal process and the resulting metal lines are recessed into a supporting material that preferably has a substantially planar surface.